InitDevice.c File Reference

#include <SI_EFM8BB1_Register_Enums.h>
#include "InitDevice.h"

Go to the source code of this file.

Functions
void	enter_DefaultMode_from_RESET (void)
void	WDT_0_enter_DefaultMode_from_RESET (void)
void	PORTS_0_enter_DefaultMode_from_RESET (void)
void	PBCFG_0_enter_DefaultMode_from_RESET (void)
void	CLOCK_0_enter_DefaultMode_from_RESET (void)
void	CMP_0_enter_DefaultMode_from_RESET (void)
void	TIMER01_0_enter_DefaultMode_from_RESET (void)
void	TIMER_SETUP_0_enter_DefaultMode_from_RESET (void)
void	INTERRUPT_0_enter_DefaultMode_from_RESET (void)
void	UART_0_enter_DefaultMode_from_RESET (void)
void	ADC_0_enter_DefaultMode_from_RESET (void)
void	TIMER16_2_enter_DefaultMode_from_RESET (void)
void	PORTS_1_enter_DefaultMode_from_RESET (void)
void	CMP_1_enter_DefaultMode_from_RESET (void)
void	VREF_0_enter_DefaultMode_from_RESET (void)

Detailed Description

generated by Hardware Configurator

This file contains device initialization.

This file will be regenerated when saving a document. leave the sections inside the "$[...]" comment tags alone or they will be overwritten!

Definition in file InitDevice.c.

Function Documentation

ADC_0_enter_DefaultMode_from_RESET()

void ADC_0_enter_DefaultMode_from_RESET ( void  )

extern

• Enable the common mode buffer

• Select ADC0.11

• SAR Clock Divider = 0x06
• ADC0 operates in 10-bit or 12-bit mode
• The on-chip PGA gain is 0.5
• Normal Track Mode

• Left justified. No shifting applied
• Disable 12-bit mode
• ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is disabled
• Perform and Accumulate 1 conversion

• The ADC will re-track and sample the input four times during a 12-bit conversion
• Burst Mode Tracking Time = 0x22

• Burst Mode Power Up Time = 0x04
• Enable low power mode
• Low power mode enabled
• Select bias current mode 3

• Enable ADC0 burst mode
• ADC0 conversion initiated on overflow of Timer 2

Definition at line 360 of file InitDevice.c.

CLOCK_0_enter_DefaultMode_from_RESET()

void CLOCK_0_enter_DefaultMode_from_RESET ( void  )

extern

• Clock derived from the Internal High-Frequency Oscillator
• SYSCLK is equal to selected clock source divided by 16

Definition at line 197 of file InitDevice.c.

CMP_0_enter_DefaultMode_from_RESET()

void CMP_0_enter_DefaultMode_from_RESET ( void  )

extern

• External pin CMP0P.8
• External pin CMP0N.1

• Comparator rising-edge interrupt enabled

• Comparator enabled

Definition at line 209 of file InitDevice.c.

CMP_1_enter_DefaultMode_from_RESET()

void CMP_1_enter_DefaultMode_from_RESET ( void  )

extern

• External pin CMP1P.8
• External pin CMP1N.5

• Comparator rising-edge interrupt enabled

• Comparator enabled
• Positive Hysteresis = Hysteresis 1
• Negative Hysteresis = Hysteresis 3

Definition at line 535 of file InitDevice.c.

enter_DefaultMode_from_RESET()

void enter_DefaultMode_from_RESET ( void  )

extern

Definition at line 25 of file InitDevice.c.

INTERRUPT_0_enter_DefaultMode_from_RESET()

void INTERRUPT_0_enter_DefaultMode_from_RESET ( void  )

extern

• Enable interrupt requests generated by the ADINT flag
• Disable ADC0 Window Comparison interrupt
• Disable CP0 interrupts
• Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags
• Disable all Port Match interrupts
• Disable all PCA0 interrupts
• Disable all SMB0 interrupts
• Disable Timer 3 interrupts

• Enable each interrupt according to its individual mask setting
• Disable external interrupt 0
• Disable external interrupt 1
• Disable all SPI0 interrupts
• Enable interrupt requests generated by the TF0 flag
• Enable interrupt requests generated by the TF1 flag
• Disable Timer 2 interrupt
• Enable UART0 interrupt

Definition at line 306 of file InitDevice.c.

PBCFG_0_enter_DefaultMode_from_RESET()

void PBCFG_0_enter_DefaultMode_from_RESET ( void  )

extern

• Weak Pullups enabled
• Crossbar enabled

• UART TX, RX routed to Port pins P0.4 and P0.5
• SPI I/O unavailable at Port pins
• SMBus 0 I/O unavailable at Port pins
• CP0 unavailable at Port pin
• Asynchronous CP0 unavailable at Port pin
• CP1 unavailable at Port pin
• Asynchronous CP1 routed to Port pin
• SYSCLK unavailable at Port pin

Definition at line 163 of file InitDevice.c.

PORTS_0_enter_DefaultMode_from_RESET()

void PORTS_0_enter_DefaultMode_from_RESET ( void  )

extern

• P0.0 is low. Set P0.0 to drive low
• P0.1 is high. Set P0.1 to drive or float high
• P0.2 is high. Set P0.2 to drive or float high
• P0.3 is low. Set P0.3 to drive low
• P0.4 is high. Set P0.4 to drive or float high
• P0.5 is high. Set P0.5 to drive or float high
• P0.6 is high. Set P0.6 to drive or float high
• P0.7 is low. Set P0.7 to drive low

• P0.0 output is open-drain
• P0.1 output is open-drain
• P0.2 output is open-drain
• P0.3 output is push-pull
• P0.4 output is push-pull
• P0.5 output is open-drain
• P0.6 output is open-drain
• P0.7 output is push-pull

• P0.0 pin is configured for digital mode
• P0.1 pin is configured for analog mode
• P0.2 pin is configured for digital mode
• P0.3 pin is configured for digital mode
• P0.4 pin is configured for digital mode
• P0.5 pin is configured for digital mode
• P0.6 pin is configured for digital mode
• P0.7 pin is configured for digital mode

• P0.0 pin is skipped by the crossbar
• P0.1 pin is skipped by the crossbar
• P0.2 pin is skipped by the crossbar
• P0.3 pin is skipped by the crossbar
• P0.4 pin is not skipped by the crossbar
• P0.5 pin is not skipped by the crossbar
• P0.6 pin is skipped by the crossbar
• P0.7 pin is not skipped by the crossbar

Definition at line 88 of file InitDevice.c.

PORTS_1_enter_DefaultMode_from_RESET()

void PORTS_1_enter_DefaultMode_from_RESET ( void  )

extern

• P1.0 pin is configured for digital mode
• P1.1 pin is configured for digital mode
• P1.2 pin is configured for digital mode
• P1.3 pin is configured for analog mode

• P1.0 pin is not skipped by the crossbar
• P1.1 pin is skipped by the crossbar
• P1.2 pin is not skipped by the crossbar
• P1.3 pin is skipped by the crossbar

Definition at line 497 of file InitDevice.c.

TIMER01_0_enter_DefaultMode_from_RESET()

void TIMER01_0_enter_DefaultMode_from_RESET ( void  )

extern

• Timer 0 High Byte = 0x80

• Timer 0 Low Byte = 0x60

Definition at line 240 of file InitDevice.c.

TIMER16_2_enter_DefaultMode_from_RESET()

void TIMER16_2_enter_DefaultMode_from_RESET ( void  )

extern

• Timer 2 High Byte = 0xE7

• Timer 2 Low Byte = 0x14

• Timer 2 Reload High Byte = 0xE7

• Timer 2 Reload Low Byte = 0x14

• Start Timer 2 running

Definition at line 442 of file InitDevice.c.

TIMER_SETUP_0_enter_DefaultMode_from_RESET()

void TIMER_SETUP_0_enter_DefaultMode_from_RESET ( void  )

extern

• Mode 3, Two 8-bit Counter/Timers
• Mode 3, Timer 1 Inactive
• Timer Mode
• Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level
• Timer Mode
• Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level

• Start Timer 1 running

Definition at line 279 of file InitDevice.c.

UART_0_enter_DefaultMode_from_RESET()

void UART_0_enter_DefaultMode_from_RESET ( void  )

extern

• UART0 reception enabled

Definition at line 349 of file InitDevice.c.

VREF_0_enter_DefaultMode_from_RESET()

void VREF_0_enter_DefaultMode_from_RESET ( void  )

extern

Definition at line 570 of file InitDevice.c.

WDT_0_enter_DefaultMode_from_RESET()

void WDT_0_enter_DefaultMode_from_RESET ( void  )

extern

Definition at line 43 of file InitDevice.c.